LorePath
  • Browse
  • ·FAQ
Back to Results

Magical Tome

Cover of Gate sizing and buffer insertion methods for optimizing delay and power in CMOS and BiCMOS logic networks
First published
1995
Pages
172 pages
ISBN
0612028046

Gate sizing and buffer insertion methods for optimizing delay and power in CMOS and BiCMOS logic networks

The outer archives are busy

by Kerry Steven Lowe

No synopsis in the archives yet.

Match Score

Create a free account to see Match Scores on books the community has marked — once you’ve set your preferences.

Create free account

Marks of the Realm

Marks left by readers of this tome

No community marks yet — be the first to inscribe this tome.

Pacing

—out of 5

Horror / Dark Elements

—out of 5

Romance

—out of 5

Spice Level

—out of 5

LGBTQ+ Representation

—out of 5

Social & Political Themes in Stories

—out of 5

Inscribe Your Rating

Mark this tome across each content category