Formal Verification of Floating-Point Hardware DesignDavid M. Russinoff, J Strother Moore · First published 2018Open the Tome
Specification and verification of gate-level VHDL models of synchronous and asynchronous circuitsDavid M. Russinoff · First published 1995Open the Tome
A formal language for the specification and verification of synchronous and asynchronous circuitsDavid M. Russinoff · First published 1993Open the Tome
