RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA designStuart Sutherland · First published 2017Open the Tome
The Organization Of The German State Forces In 1866Stuart Sutherland · First published 2011Open the Tome
SystemVerilog for designSutherland, Stuart., Stuart Sutherland, Simon Davidmann, Peter Flake · First published 2003Open the Tome