RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA designStuart Sutherland · First published 2017Open the Tome
Software Defined Radio using MATLAB & Simulink and the RTL-SDRRobert W Stewart, Kenneth W Barlee, Dale S W Atkinson, Louise H Crockett · First published 2015Open the Tome
Digital design, with RTL design, VHDL, and VerilogFrank Vahid · First published 2010 · Latest edition 2011Open the Tome
Principles of verifiable RTL designLionel Bening, Harry D. Foster · First published 2000Open the Tome